It seems that after a very short-lived DolphinDOS 1 and the immense success of DolphinDOS 2, cool dudes who made it all possible had to face their first difficulties. As version 1 and 2 depended on the presence of a completely unused (all eight bits) 6522 VIA parallel port, this became a major blocker when Commodore couldn’t decide on how to make 1541 less annoying (and potentially less failure prone) with the notorious head banging over the wall of stepper stop. Not only those strange efforts never yielded any well working results in the end (some say quite the opposite) but to make things even worse, remnants of the ill approach took one port bit out of the equation. This happened with the release of 1541C (often considered as the worst/least compatible 1541 model ever made) and was then carried over all the way up to the 1541-II. Although that last revision of the device had most of the problems of the earlier incarnations ironed out - it still wastes (has it grounded) one bit of the VIA port, even if the final ROM revision doesn’t need this lameness anymore. This fact led to speculations that maybe some early 1541-II units were shipped still with 1541C ROM contents but I admit I never encountered such combination, nor heard of anyone who did.
Although after DolphinDOS 2, for some time Dolphin Software offered various versions for different computers and drives, at that moment, having no easy way to provide the parallel connection between the drive and the host computer anymore, DolphinDOS creators had to think of a different approach. Their farsighted response of the next (1987) year was to provide their own port by adding an appropriate, commonly used peripheral IC to the drive-side hardware. Their choice was a Motorola’s 6821 PIA chip, which had already been used for some time in various designs. This resolved the most burning problem and allowed DolphinDOS 3 to be applicable to all versions of the drive. Unfortunately the solution didn’t come for free. And I don’t mean only the price of the additional PIA IC! While earlier DolphinDOS versions could easily use software written for SpeedDOS style parallel connection, version 3 became immediately incompatible with all of it. Due to different address mapping, some software positions written for DolphinDOS 2 didn’t work anymore either. As if it wasn’t enough, it seems (note: a very subjective feeling, backed only partially with various, hand measured operations time) that DD3 is slightly (I mean really marginally) slower in operation than DolphinDOS 2. I am not sure where this difference may stem from. One thing, which is different between versions 2 and 3, is the way, in which the PIA chip has to be programmed when using its parallel ports. While 6522 VIA has separate DDR and port registers, in the PIA both functions are combined in one register, and the actual function is selected by writing values to another one. This means that with 6522, one write was needed to set DDR and another one could already put data on the port bits. With PIA one write is needed to select the function of the register, second write is needed to set DDR values and only third can put bits on the port. Similar situation (and difference in CPU cycles) happens when reading bits from the port. As I already mentioned - I am not really sure if this fact could have had enough impact to make a perceivable difference for the end user but I don’t see anything else that could. Well... I am not really sure if the difference is indeed perceivable ;-)
Everything written in this section about DolphinDOS 2, remains valid for version 3. Even the KERNAL ROM content remains fully compatible. To tell the full truth, I never had original DD3 KERNAL and always used the one, which came with my first DD2 purchase.
The drive-side hardware is OTOH a very different beast. Of course VIA got swapped with another major, 40-pin IC, but also the supporting logic was vastly extended, effectively doubling the number of 74LS chips from three to six. To be completely frank - whenever I look at the schematic below, I have the feeling that it is unnecessarily overcomplicated. Why is it done so? First of all, the PIA chip had to be given its own address range. Yet this alone does not justify such a big difference, does it? When you take a closer look at how the address lines are handled, it becomes visible that RAM chip will be selected whenever
- A13 == HI
- A14 == HI
- A15 == LO
- A12 == HI
- A13 == LO
- A14 == HI
- A15 == LO
Here comes the schematic:
And the PCB:
PCB had to grow in order to carry all those additional ICs, and so it did. It became noticeably bigger. To achieve flexibility in locating the PCB inside target devices, it no longer gets placed and connected directly over the 6502/6522 sockets but uses (talking about flexibility, huh?) flexible 40-wire ribbon cable and an IDC to IC socket adapter, which has to be placed in the 6502 CPU socket. As everything, flexibility has its price though. This non-shielded ribbon cable carries now virtually all digital activity of the system over a non-negligible distance. Depending on how it is eventually routed in relation to other electronic components this may become a source of severe headaches! While I didn’t want to just copy the original layout, I have to admit that I found it somewhat challenging to lay the PCB out the way I would be happy with. Even with its bigger routing area, I still couldn’t get fully satisfied with consecutive outcomes. I had to eventually settle down though and the result can be seen above (rev.1a). In the download section further down the page, there are GERBER files (rev.1b - minor improvements) available for download, which can be used to produce the pictured PCB. In case you want a ready made one, please check the For Sale section and/or contact me.
- JP1 is used to turn the expansion ON/OFF
- This version has to be installed differently of course, and I very much suggest placing strong isolating element below the PCB in order to avoid the highly unwanted contact of the pins with other, electrically active elements...
- Please mind where and how you route the cable when installing the board! At CBM it was the job of PCB designers to route the signals properly, avoiding unwanted interference. True - there were cases when they didn’t do a good job either but here it is you and only you who have to take proper care of it yourself! One friend from Finland installed his DolphinDOS3 board in a 1541-C drive (yes, that most loathsome version ;-) He found a nice place for it in front of the controller’s main board, right over the drive’s mechanism. Everything looked perfectly well, but... didn’t work equally well! All kind of read/write errors and complete lack of reliability of operations. The reason? I believe the CPU ribbon cable routed close over the analogue circuits of the drive to be the culprit. I believe that all the digital activity radiating off the cable might have interfered with minuscule analogue currents’ flow. It eventually occurred that wrapping the CPU cable in a copper foil made the problems disappear.
- dd3_schematic_rev1d-0.png - schematic of the drive-side hardware
- dd3_gerbers_rev1b-0.zip - GERBER files for producing the PCB
- 3dosa_c_27c256_payload.bin.zip - Drive-side firmware
- dd2_kernal_rom.bin - KERNAL ROM (original DD2 - with CBM compatible blue on blue colours)
- sd_dd2_kernal_rom.bin - KERNAL ROM (DD2 customised with my preferred startup colours and message :-)
- 6821.pdf - MC6821 datasheet (over 1MiB)
- Replay Resources wiki
- Dolphin DOS - Flinker Delfin (German)
- Dolphin DOS 2.0 - und es läuft und läuft und läuft... (German)
- DolphinDOS at C64-wiki (German)
- DolphinDOS manual at project64.c64.org