The schematic:


Everything clear, right? Please note that unlike many other adapters, here we control the activity of the EPROM with both the CS (CE) and OE lines. This very simple design choice (implemented thanks to Gerrit Heitsch suggestion!) allows reduction of power consumption by factor 200 (!) whenever the chip is not accessed! While this means that valid data will appear on the bus some ns later than in case of controlling only the output drivers with OE line, this delay does not affect normal operations with all reasonably fast ICs. If you by chance run into trouble (I haven’t with neither 100 nor 200ns EPROMs) with an unusually slow chip, I rather suggest replacing the chip than cutting the traces... Actually, maybe I may put a jumper for this one day.. who knows?

The PCB:



  1. IMPORTANT! This is designed for all "wide" boards of the 64 with 0.8" ROM ICs placement raster. Those include ASSY# 250407, 250425, 250441, 250466. It does NOT fit into boards with 1.0" ROM ICs placement raster like ASSY# 326298 and KU14194HB. For those a separate version is in the works...
  2. Assembled PCB is to be press-fit placed in the KERNAL ROM socket with two single-pin points marked as BASIC and CHAROM, tapping on pins 20 of BASIC and CHAROM IC’s sockets respectively. If your original ROMs were not socketed, you may decide to solder the above PCB in. I have to say, however, that I find little to no excuse for not soldering good sockets in place of the original chips, once those are removed
  3. Default CHAROM/KERNAL images are active when no jumpers are attached to the CHAROM/KERNAL pinheads or attached switches are in their “open” position
  4. ROM content is to be laid out as shown here (supplied GERBER files have this map in the silk-screen too):